Using Bayesian networks to accurately calculate the reliability of complementary metal oxide semiconductor gates

Walid Ibrahim, Valeriu Beiu

    Research output: Contribution to journalArticlepeer-review

    39 Citations (Scopus)

    Abstract

    Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gate's topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gate's overall reliability.

    Original languageEnglish
    Article number5953545
    Pages (from-to)538-549
    Number of pages12
    JournalIEEE Transactions on Reliability
    Volume60
    Issue number3
    DOIs
    Publication statusPublished - Sep 2011

    Keywords

    • Bayesian network
    • CMOS transistors
    • design automation
    • digital circuit
    • nanotechnology
    • reliability modeling

    ASJC Scopus subject areas

    • Safety, Risk, Reliability and Quality
    • Electrical and Electronic Engineering

    Fingerprint

    Dive into the research topics of 'Using Bayesian networks to accurately calculate the reliability of complementary metal oxide semiconductor gates'. Together they form a unique fingerprint.

    Cite this