After a short review of the state-of-the-art, a new low-power differential threshold logic gate is introduced: split-precharge differential noise-immune threshold logic (SPD-NTL). It is based on combining the split-level precharge differential logic, with a technique for enhancing the noise immunity of threshold logic gates: noise suppression logic. Another idea included in the design of the SPD-NTL gates is the use of two threshold logic banks implementing f and f_bar, and working together with the noise suppression logic blocks for enhanced performances. Simulations in 0.25 μm CMOS @ 2.5 V show the functionality of the gate up to 2 GHz. An advanced layout based on high matching centroid techniques is currently under development.