Reliability of NAND-2 CMOS gates from threshold voltage variations

Walid Ibrahim, Valeriu Beiu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)

    Abstract

    The high-level approach for estimating circuit reliability tends to consider the probability of failure of a logic gate as a constant, and work towards the higher levels. With scaling, such gate-centric approaches become highly inaccurate, as both transistors and input vectors drastically affect the probability of failure of the logic gates. This paper will present a transistor-level gate failure analysis starting from threshold voltage variations. We will briefly review the state-of-the-art, and rely upon freshly reported results for threshold voltage variations. These will be used to estimate the probabilities of failure of a classical NAND-2 CMOS gate for (a few) different technologies, voltages, and input vectors. They will also reveal huge differences between the highest and the lowest probabilities of failure, and will show how strongly these are affected by the supply voltage.

    Original languageEnglish
    Title of host publication2009 International Conference on Innovations in Information Technology, IIT '09
    Pages135-139
    Number of pages5
    DOIs
    Publication statusPublished - 2009
    Event2009 International Conference on Innovations in Information Technology, IIT '09 - Al-Ain, United Arab Emirates
    Duration: Dec 15 2009Dec 17 2009

    Publication series

    Name2009 International Conference on Innovations in Information Technology, IIT '09

    Other

    Other2009 International Conference on Innovations in Information Technology, IIT '09
    Country/TerritoryUnited Arab Emirates
    CityAl-Ain
    Period12/15/0912/17/09

    ASJC Scopus subject areas

    • Information Systems

    Fingerprint

    Dive into the research topics of 'Reliability of NAND-2 CMOS gates from threshold voltage variations'. Together they form a unique fingerprint.

    Cite this