Parallel and serial repeater-insertion strategies use, respectively, parallel and serial repeaters to minimize the propagation delay over global SoC interconnects. General performance trade-offs refer to any combination of silicon area (Area), delay (T), power (P), energy (E) and reliability. In this paper we address the VLSI designs performance metrics within the repeater-insertion strategies. We study the effect of modeling the power, reliability, as well performance trade-offs on the area-delay optimum found using the repeater-insertion strategies. Simulation results using a 0.25 μm TSMC technology show that the parallel repeater-insertion strategy starts achieving a better speed than the non-regenerated interconnect at wire lengths smaller than that achieved when the interconnect is serially regenerated. It also features a 47% time delay saving and a 96% Area-Delay product saving over the serial repeaterinsertion strategy.