The latest results on biasing (upsizing) the gate lengths of CMOS transistors implemented in advanced technologies have identified optimum lengths which allow maximizing the static noise margins (SNMs). The optimum lengths for nMOS and pMOS transistors were determined analytically, based on BSIM4v4.7.0 equations for the threshold voltage. Further, it has been shown through simulations that designs using such optimum lengths exhibit better performances than those obtained using classical design methods (minimum length transistors). In this paper, we will present for the first time detailed Monte Carlo (MC) simulations for estimating the SNMs of XOR-2 and MAJ-3 CMOS gates when implemented in 22nm predictive technology models (PTM). These support the claim that the SNMs of CMOS gates using optimally sized transistors are significantly (about twice) better than the SNMs of classically sized CMOS gates, for any input combinations.