Low power soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline

Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah Awwad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Advancement in deep submicron (DSM) technologies led to miniaturization. However, it also increased the vulnerability against some electrical and device non-idealities, including the soft errors. These errors are significant threat to the reliable functionality of digital circuits. Several techniques for the detection and deterrence of soft errors (to improve the reliability) have been proposed, both in synchronous and asynchronous domain. In this paper we propose a low power and soft error tolerant solution for synchronous systems that leverages the asynchronous pipeline within a synchronous framework. We named our technique as macro synchronous micro asynchronous (MSMA) pipeline. We provided a framework along with timing analysis of the MSMA technique. MSMA is implemented using a macro synchronous system and soft error tolerant and low power version of null convention logic (NCL) asynchronous circuit. It is found out that this solution can easily replace the intermediate stages of synchronous and asynchronous pipelines without changing its interface protocol. Such NCL asynchronous circuits can be used as a standard cell in the synchronous ASIC design flow. Power and performance analysis is done using electrical simulations, which shows that this techniques consumes at least 22% less power and 45% less energy delay product (EDP) compared to state-of-the-art solutions.

Original languageEnglish
Title of host publicationProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
PublisherIEEE Computer Society
Pages601-606
Number of pages6
ISBN (Electronic)9781479937639
DOIs
Publication statusPublished - Sep 18 2014
Event2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States
Duration: Jul 9 2014Jul 11 2014

Other

Other2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
Country/TerritoryUnited States
CityTampa
Period7/9/147/11/14

Keywords

  • Low power Aynshronous circuits
  • NCL pipeline
  • SE tolrerant circuits
  • Soft Error

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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