High performance fast multiplier

G. M. Chaudhary, F. Kharbash

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Binary multiplication is very crucial arithmetic operations in digital signal processing systems as well as general computer systems because the performance of the processor is significantly influenced by the speed of their multipliers. In this paper, we present a design-methodology for high-speed multiplications, where two integers of n-bit size each are multiplied to produce a 2n-bit product. This paper presents an efficient method for performing multiplications in one step from the least significant bit towards the most significant bit.

Original languageEnglish
Title of host publication2008 IEEE Region 5 Conference
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE Region 5 Conference - Kansas City, MO, United States
Duration: Apr 17 2008Apr 20 2008

Publication series

Name2008 IEEE Region 5 Conference

Other

Other2008 IEEE Region 5 Conference
Country/TerritoryUnited States
CityKansas City, MO
Period4/17/084/20/08

Keywords

  • Carry-adders
  • High performance fast multiplier
  • Least signifying bet
  • Most significant bit
  • Overflow
  • Partial products
  • Product term
  • Product values

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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