Hardware Trojans in asynchronous FIFO-buffers: From clock domain crossing perspective

Syed Rafay Hasan, Siraj Fulum Mossa, Ciro Perez, Falah Awwad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

System on chip (SoC) contains multiple intellectual properties (IPs) that work in different clock domains. Several of those IPs may even have multiple clock domains within itself and provided to SoC designers as hard IPs. Different clock domain crossing (CDC) techniques are used to communicate among different clock domains. First In First Out (FIFO) buffers are part of several CDC circuits. This research explores the possible security vulnerabilities of such SoCs in the event of compromised security in FIFO buffers. We investigated few catastrophic possibilities of hardware Trojans in FIFO buffers and discussed its potential consequences. Testing the design using random bit generation showed that the triggering probabilities of such Trojans are less than 8/1000. Our synthesis results show that majority of these Trojans require minimal area and frequency overhead, in the range of.8% and 1%, respectively, if FIFO occupies 10% space of the IP.

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-September
ISBN (Print)9781467365574
DOIs
Publication statusPublished - Sep 28 2015
Event58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015 - Fort Collins, United States
Duration: Aug 2 2015Aug 5 2015

Other

Other58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015
Country/TerritoryUnited States
CityFort Collins
Period8/2/158/5/15

Keywords

  • clock domain crossing
  • First In First Out (FIFO)
  • Hardware Trojan

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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