The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(log 2N). Lastly a fresh algorithm which reduces the size to polynomial is suggested.
|Title of host publication||International Conference on Young Computer Scientists|
|Publication status||Published - Jul 15 1993|
|Event||ICYCS'93 - Beijing, China|
Duration: Jul 15 1993 → …
|Period||7/15/93 → …|