Design layout optimization in the presence of proximity-dependent stress effects

Akif Sultan, Rashad Ramzan, Derick Wristers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we present Minimized Layout Effect (MINLAYEF) guidelines for reducing the layout and process variations in critical analog circuits. We also present digital design guidelines to minimize the effect of process variations by eliminating stress sources. We also propose a layout for a reference device for a dual stress liner (DSL) device architecture to improve the accuracy of simulations. Si results from circuit layout designed with and without layout guidelines are also presented.

Original languageEnglish
Title of host publicationICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology
PublisherIEEE Computer Society
ISBN (Print)9781479921539
DOIs
Publication statusPublished - Jan 1 2014
Event2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014 - Austin, TX, United States
Duration: May 28 2014May 30 2014

Publication series

NameICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

Other

Other2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014
Country/TerritoryUnited States
CityAustin, TX
Period5/28/145/30/14

Keywords

  • DSL
  • Layout guidelines
  • Stress proximity effects

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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