Considerations for phase accumulator design for direct digital frequency synthesizers

David J. Betowski, Valeria Beiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to generate high-resolution, fast switching frequencies for modem communication systems. Because these systems are required to have high speed and/or low power requirements, optimizing the phase accumulator (PA) component is a crucial design step. A mathematical model for estimating the speed-power tradeoffs of pipelined PAs will be presented. Simulations based on this model show that pipelining the PA to the maximum allowable number of stages provides the smallest latency, but at power consumptions significantly higher than a non-pipelined PA. The model can be used to estimate the optimal number of pipeline stages for given speed-power constraints.

Original languageEnglish
Title of host publicationProceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Pages176-179
Number of pages4
DOIs
Publication statusPublished - 2003
Externally publishedYes
Event2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China
Duration: Dec 14 2003Dec 17 2003

Publication series

NameProceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Volume1

Other

Other2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Country/TerritoryChina
CityNanjing
Period12/14/0312/17/03

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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