Characterization of a 16-bit threshold logic single-electron technology adder

M. Sulieman, V. Beiu

Research output: Contribution to journalConference articlepeer-review

18 Citations (Scopus)

Abstract

Single electron technology (SET) is one of the future technologies distinguished by its small and low-power devices. SET also provides simple and elegant solutions for threshold-logic gates (TLGs). This paper presents the design of an optimal TLG adder implemented in SET. This 16-bit Kogge-Stone style adder was fully designed and simulated using a Monte Carlo simulator. The simulation results give a quantitative estimate of both the delay and the power dissipation of the adder. The characteristics of our novel adder are compared with recent results estimating the energy-delay characteristics of advanced CMOS adders.

Original languageEnglish
Pages (from-to)III681-III684
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
Publication statusPublished - 2004
Externally publishedYes
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: May 23 2004May 26 2004

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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