Automating the sizing of transistors in CMOS gates for low-power and high-noise margin operation

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    4 Citations (Scopus)

    Abstract

    This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan-in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold-voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi-faceted gains, however, do incur some performance loss.

    Original languageEnglish
    Pages (from-to)1637-1654
    Number of pages18
    JournalInternational Journal of Circuit Theory and Applications
    Volume43
    Issue number11
    DOIs
    Publication statusPublished - Nov 2015

    Keywords

    • CMOS
    • PID feedback control
    • energy consumption
    • logic gates
    • power dissipation
    • static noise margin
    • transistor sizing

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Computer Science Applications
    • Electrical and Electronic Engineering
    • Applied Mathematics

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