Currently, with device geometries shrinking below 28nm, the available reliability margins of CMOS designs are drastically being reduced. This massive scaling deep into the nanometer range, will make the manufacture of future nano-circuits extremely complex and will introduce more defects, and more transient faults are expected to appear during operation. Hence, accurately calculating the reliability margins of future nano-circuits will become very critical for optimizing the trade-offs between the conflicting metrics of area-power-delay versus reliability. However, accurately calculating the reliability margins of large and highly connected circuits is a complex and very time consuming process. This paper presents an efficient and accurate solution for estimating the reliability of digital combinational circuits. The simulation results show that the solution is accurate enough and scales well with the circuit size and the length of the input vector.